Intel to unveil energy-efficient, many-core research chip
- 17 November, 2009 06:52
Nearly two years after unveiling its experimental 80-core chip, Intel Corp. is getting ready to show off its next incarnation of a high-powered, energy-efficient many-core research chip.
Intel is developing a many-core chip designed to dramatically improve energy efficiency in the data center and for the cloud, according to Justin Rattner, CTO and senior Intel fellow. Intel plans to unveil the research chip before the end of the year, he said.
Rattner told Computerworld the company plans to unveil the new chip before the end of the year. The chip, which is experimental and not commercially ready, has a "completely new design" and a high core count. While the last experimental chip had 80 cores , Rattner said this one won't necessarily have the same number, but it will have many more cores than chips currently on the market.
"We all know there are a couple of challenges to building these chips of the future , " said Andrew Chien, vice president of research and director of future technologies research at Intel Labs. "How do you scale performance in this heat envelope? We're trying to figure out how to continue to deliver more and more performance in the same kinds of packages and the same kinds of energy envelopes ... We need to continue to be building these research prototypes with the research community."
David O'Hallaron, director of Intel Labs in Pittsburg, described the new research chip as a "cluster on a chip." This incarnation of the 80-core experimental chip might not have more, nor even as many, cores, but it will be far more functional and programmable than the cores on its predecessor.
Intel's 80-core research chip had teraflop performance capabilities but used less energy than a quad-core processor. Researchers created the prototype to figure out the best way to make that many cores communicate with each other. They also were creating new architectural designs and new core designs.
At the time, Intel said it was five to eight years away from building a fully functional, commercial-ready 80-core chip.
Late last week, Rattner said they're even closer on that calculation.
"We're actually doing better than we had even predicted then," he said. "The 80-core was much more of a physical design exercise, where we were looking at power management and different ways to interconnect the processors. The new one is really designed to be generally programmable -- more of a precursor to a future commercial design. This step is [about whether we can] make a many-core chip that is more real-world usable. It's still experimental but closer to commercial."
As with the previous 80-core chip, this new research chip will stick with a very simple core, potentially dozens of very simple cores, Rattnew said. He explained that while the cores may be less powerful than the cores in dual-core or quad-core machines, the sheer number of them will make up for that while also making the chip more energy efficient.
For instance, if only a certain number of cores are needed for a job, they could run while the other cores are idle. When the cores being used start to heat up, they could be shut down and cool idle cores could take over running the job.
"We're staying with the idea of simpler cores -- this emphasis on lower performance but very energy efficient cores in substantial numbers," said Rattner. "There's a lot of interest in these new architectures as a way to dramatically improve energy efficiency in data centers . That's one area that has our interest and has definitely influenced our experimental work to try to understand what, in some sense, would be an optimized architecture."
Where the last experimental chip lacked basic functionality, this new chip is designed to have more programmable cores.
"This is less of a focus on the physical design issues and more looking at the architectural issues and the programming associated with many cores," said Rattner, who added that they're "giving some thought" to making the new chip available to researchers and academics to study how to make software parallel enough to take advantage of so many cores.