AMD spins Moore's Law in IT's favour
- 11 February, 2009 13:50
In 64-bit servers, AMD and Intel will soon be on the same page, architecturally speaking. But these similar ends were reached by very different means.
AMD carefully and selectively built on the Opteron core and total system architecture it created six years ago. In that same span of time, Intel has had to wipe its Xeon engineering slate clean twice: Once to abandon NetBurst (Pentium 4) to begin anew with a Pentium III-based CPU core called Core, and a second time to rip and replace everything outside the Core 2 core to create a completely new system architecture.
AMD's Opteron core and system design have remained intact and relevant for far longer than most interpretations of Moore's Law suggest is possible. Intel's tumultuous path to the x86 present is predictable, given the tumult that typified major turning points in x86's history. The scratch building that Intel has done in the past six years would seem to me perfectly rational, unavoidable, and even beneficial in light of Moore's Law -- were it not for the fact that AMD has lived under the same law and managed to maintain design continuity. No major component of AMD's total 64-bit server architecture has had to be remade in order to secure the platform's future.
Neither of Intel's disruptive redesigns was frivolous. Intel's need for a new core grew out of the reality that NetBurst couldn't be pushed any faster without excessive heat and poor yields. Intel's need for a new overall system design (peripheral, memory, and interprocessor buses) was born of the reality that the standard Intel bus design was a severe choke point for more efficient Core 2 CPUs. That generational race between CPU and bus is par for PCs; you could plot no course from NetBurst Xeon to the present without enormous upheaval.
Somehow AMD has managed to live under the same Moore's Law without having any element of its Opteron system architecture outpace or obsolete the rest. This is in accordance with AMD's unorthodox contract with customers, which holds that evolution of AMD's server platforms will proceed in a competitively brisk manner, but on as nondisruptive a path as possible. From AMD's perspective, its customers are its OEMs, makers of the branded servers that IT buys. OEMs love AMD's approach. Their manufacturing processes don't need to be reworked to accommodate new CPUs. AMD's OEMs are spared radical reengineering and can get new systems to market more quickly and cheaply.
In AMD's world, Moore's Law still holds sway, but it manifests differently, and the reason is simple: Opteron started with a cohesive system design, any part of which could scale without the need for replacement. AMD engineers thought through the headroom questions -- at what point will a future Opteron be throttled by its bus, and how fast can the bus be driven within noise, distance, and voltage limits?
Page BreakWhat occurred to AMD then, and which was a radical and dangerous idea, was that everything about PCs' total system architecture was wrong. The notion of a unified bus was discarded in favor of multiple independent buses driven not by external chips, but by the processors themselves. Simple, quiet HyperTransport replaced messy parallel buses. No Opteron server is recognizable as a PC, but AMD's obsessive adherence to an optional, well-publicized extension of the x86 ISA (Instruction Set Architecture) leaves software happily ignorant of its dramatically remodeled surroundings.
This topic came to mind while I was setting up a four-socket (4P), quad-core Shanghai Opteron system for testing with Windows Server 2008. The server astounds me. I delight in the incongruity of running a 16-way server on the power of a four-way workstation, and the fact that support for such a new design is already baked into a retail Windows release. The server fans roar at power up, as all 4P systems' fans do, but once it boots, active power management spins the fans down to a hush that is inaudible through the door of my GizMac XRackPro. That's a first for a top-end 4P machine. The server's BIOS has the speed and voltage tweakability (I'm an underclocker) of an enthusiast PC.
There is so much in this Shanghai server that's new, and yet the machine is as familiar to me as every Opteron server I've laid hands on since the original. As a technologist, it's exciting, in a way, to explore a design overhauled by necessity -- looking for improvements, finding the switches that enable them, and doing generational comparisons. As an IT person, it's more satisfying to plug a new Opteron server in next to its predecessor and note nothing but that it's faster and quieter. And to know that if the need arises, I can swap parts, even CPUs, among servers to maintain and reapportion my server assets. That's exactly how AMD set it up, and that's the approach I prefer.