Intel is planning to introduce a faster front-side bus on an upcoming version of its Pentium 4 Extreme Edition processor that will help the firm increase the performance of its chips by improving a crucial bottleneck in system performance.
According to an internal document on Intel's Web site first spotted by The Inquirer, Intel will soon release the 925XE chipset, a version of its recently introduced 925X chipset with support for a 1066MHz front-side bus. Current Pentium 4 chipsets use an 800MHz front-side bus to connect the processor to the memory. This is a vital link, or bottleneck, that plays an important role in determining the overall performance of a system.
Intel will also release a 3.46GHz Pentium 4 Extreme Edition that supports the 1066MHz front-side bus in the near future, according to a separate document found on Intel's site. This chip will also come with 2M bytes of Level 3 cache, just like its counterparts in the Pentium 4 Extreme Edition category.
The Pentium 4 Extreme Edition chip is Intel's performance leader for desktop PCs. But that performance comes at a premium, as the chip costs more than twice as much as the most powerful Pentium 4 processor. It is marketed almost exclusively to gamers.
An Intel spokesman declined to comment on unannounced products.
In previous years, Intel relied on ever-increasing clock speeds to improve the performance of its chips. Over the last year, the company has used other methods such as hyperthreading and cache memory to improve performance as thermal concerns brought on by the arrival of the 90-nanometer process generation have made it more difficult to rely on pure clock speed. However, Intel still needs to marginally increase clock speeds to help improve performance.
Most chip designers feel that the once the clock speed of the processor exceeds four or five times the speed of the front-side bus, the processor is charging ahead of the bus and wasting time waiting for the bus to feed it data, said Dean McCarron, principal analyst with Mercury Research.
With an 800MHz front-side bus on its 3.4GHz chips, Intel was coming up against that limit, McCarron said. A faster bus will allow the company to increase the clock speed of its chips and take full advantage of those extra clock cycles, he said. Intel has promised to release a 4GHz Pentium 4 chip in the first quarter of 2005, a mark it had expected to hit this year.
Other companies, most notably Intel rival Advanced Micro Devices (AMD), have changed their designs to include an integrated memory controller. This design removes the complexity of the memory controller from the chipset and puts it directly on the processor, reducing the latency experienced by signals as they travel from the memory to the processor, McCarron said. Latency is a measure of how quickly signals move around a circuit and designers strive to keep latency to a minimum.
For Intel's part, its front-side bus design gives it more flexibility as memory standards change, McCarron said. The industry is expected to slowly transition from DDR (double data rate) memory to DDR2 memory throughout 2005. AMD will have to make a minor adjustment to its chips to take advantage of DDR2 memory, while Intel can include support for DDR2 memory in the chipset, he said.
Like the rest of the industry, Intel has staked its future on multicore processors designs as the wave of the future. Multicore designs will place even greater demands on the front-side bus or integrated memory controller, and both Intel and AMD will need to continue to improve the performance of their designs to keep up with those demands, McCarron said.
Intel has not said anything about its future plans for the front-side bus architecture, but it appears the company will keep that design in place at least through the remainder of 2004.
Many analysts and industry observers believe the Pentium 4 architecture that has carried the company for almost five years is on its last legs. Sources expect Intel will eventually adopt its Pentium M architecture across its products, which delivers more performance at slower clock speeds.