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Via readies 64-bit capability for Isaiah

Via readies 64-bit capability for Isaiah

Via Technologies will add 64-bit capabilities into Isaiah, a multimedia processor core design expected to arrive in 2006, the company plans to announce Tuesday at the Fall Processor Forum in California.

Isaiah will target the consumer electronics and high-definition computing markets when it is released in 2006, said Glenn Henry, president of Centaur Technology, Via's processor design subsidiary. Via currently sells about half its processors to low-cost PC vendors and the other half to embedded device manufacturers, and it expects Isaiah to attract attention from both sets of customers, he said.

The new chip will use the same 64-bit extensions to the x86 architecture that Advanced Micro Devices Inc. (AMD) developed and Intel Corp. later adopted, Henry said. The x86 instruction set was developed by Intel more than 20 years ago, but AMD was the first company to add 64-bit extensions. The majority of the world's software for PCs uses that instruction set.

"Our strategy all along has been perfect compatibility with software. In the case of 64-bitness, it makes no sense to deviate from the architectural standard that has been developed," Henry said.

The company was also adamant that it design a brand-new chip for the 64-bit generation of processors, like AMD's approach, Henry said. Intel added 64-bit capabilities into an existing processor design.

"We felt to do it right, it needed to be done from scratch. We had the time, it was not an urgent need in our marketplace," Henry said.

Via targets a wide range of PC and thin-client vendors that are less concerned with performance and more interested in low-cost and low-power chips, Henry said. For that reason, Via has yet to announce a strategy for moving to dual-core designs, he said.

Intel and AMD are joining the server processor world in moving toward dual-core designs to increase performance. Increasing a processor's clock speed to improve performance is now unfashionable in the chip design community as the industry pays closer attention to power consumption.

Via's customers don't need the bleeding-edge performance that Intel and AMD are attempting to produce, Henry said. Via will eventually design and release a dual-core chip, but that product is significantly far out in the future, he said.

However, performance was the goal of Via's improvements to the processor's floating-point unit, Henry said. Isaiah's floating-point performance will be "several factors" beyond the floating-point performance of Via's current products, he said. Improved floating-point capabilities will allow Isaiah to process complex video and computer graphics to improve the performance of games and other multimedia applications, he said.

The Taipei company is sidestepping another architectural debate among chip designers in this market by using both an integrated memory controller and a classic front-side bus design on Isaiah, Henry said.

AMD uses an integrated memory controller on its Opteron and Athlon 64 chips to speed up the rate that signals travel between the memory and the processor. This has given AMD great benchmark scores on memory-intensive applications, but locks the company into one type of memory, Henry said. A processor with an integrated memory controller must be redesigned to accommodate new memory types, such as the transition between DDR (double data rate) and DDR2 memory that is expected to occur in 2005.

Intel's front-side bus approach adds latency to the motherboard, but allows the processor to work in multiple chipset and motherboard configurations with multiple memory types, Henry said. Isaiah's customers will be able to configure their processor and chipset with either a front-side bus or an integrated memory controller depending on the types of applications for which the processor will be used, he said.

Isaiah will follow Esther, Via's 90-nanometer processor that is expected to arrive in the first quarter of 2005, Henry said. Esther will be built on IBM's 90-nanometer process technology in East Fishkill, New York. It will run at 2GHz with an 800MHz front-side bus, he said.

Henry is expected to present additional details about Isaiah and Esther during the Fall Processor Forum at San Jose's Fairmont Hotel. Sponsored by market research firm In-Stat/MDR, Tuesday's sessions at the Fall Processor Forum will also feature technology disclosures from AMD, Transmeta, Sun Microsystems, Fujitsu, and many other chip companies.


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