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AHEAD OF THE CURVE: Itanium is Intel's future

AHEAD OF THE CURVE: Itanium is Intel's future

Intel racked up some serious karmic debt when it schemed to run Advanced Micro Devices (AMD) out of the PC processor business. Xeon now languishes in Opteron's shadow, which strikes me as just desserts for some nasty business. Now is a good time for Intel to send up some mea culpas and grab some focus. Instead, Intel is pursuing a reactive strategy.

It's obsessing about keeping pace with AMD's engineering when it should be focusing on its unique properties.

PC customers will welcome dual-core Xeon just as they have Nocona. It is the next bump of a familiar architecture whose vital signs are slowly fading. But if it costs less than what Xeon's customers would have paid anyway, customers will buy it.

Yet customers won't pay any more for dual-core Xeon servers than they will for the dual-core Opteron servers - which are likely to beat Intel's new boxes to market - or for the dual-core PowerPC that I expect to see next year. Again, Intel must focus on its unique properties rather than make noise about using denser manufacturing processes to pack more transistors onto one die.

Intel should conserve its engineering effort and its marketing dollars, and it should invest in properties that competitors can't match: Itanium and software. Itanium gets short shrift in the press for lousy sales, but Intel's right when it calls Itanium the architecture for the next 20 years. Or at least Itanium is a good example of the architectures that will survive after x86 and PowerPC have left the scene.

Intel chose the controversial and underappreciated very long instruction word (VLIW) design for Itanium.

Instead of using x86's grossly complicated and fallible techniques for rearranging a queue of instructions to make best use of the CPU's concurrent resources, every VLIW instruction explicitly and simultaneously targets multiple processor execution units.

Responsibility for optimal execution is not the processor's job, but the compiler's. It builds instructions for every operation, and if the compiler does its job properly, all of the processor's resources are constantly occupied.

Transmeta's Efficeon is another VLIW CPU that attests to the concept. Transmeta uses VLIW to emulate an x86 processor, but uniquely, Efficeon's compiler is effectively inside the chip. It adapts its operation to running applications' x86 instruction mix; the longer it runs, the faster it runs by packing more simultaneous operations into each VLIW instruction.

Intel built Itanium just to do the VLIW thing. It didn't build a compiler inside, but Intel has something better: its own compilers. Intel's C++ and Fortran compilers are already great at squeezing the maximum power out of its x86 processors. The CISC design of x86 has nothing in common with Itanium's VLIW design, but Intel's long compiler experience leaves the vendor with a deep bag of tricks.

It will fall to Intel to make its Itanium compilers not merely functional but exceptional. Intel has to build compilers that generate deadly code for operating systems designed for serial execution.

That's no small challenge, but Intel is equal to the task. Unless, that is, Intel continues to obsess about x86 to the detriment of its engineering investment in the products that can return it to the front of the pack.


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