IBM will deliver its next-generation Power5 RISC microprocessor architecture sometime in mid-2004, according to company officials at the IBM PartnerWorld event in New Orleans.
The processors will deliver roughly four times the performance of current-generation Power4 chips and will feature technologies that support application-specific performance boosts and mainframe-like partitioning capabilities.
Power5 chips will feature a technology called simultaneous multi-threading that will enable up to 80 per cent better application-level performance than current technologies permit, vice-president of IBM's pSeries product group, Karl Freund, said.
Simultaneous multi-threading technology built on the capabilities available in today's dual-core Power4 processor architecture, Freund said.
Dual-core processors featured two processors packed into one piece of silicon, he said. With simultaneous multi-threading, each of the processors in a dual-core chip would be capable of running two separate processes or tasks at the same time, thereby greatly boosting performance.
The Power5 architecture would also introduce a mainframelike subprocessor partitioning capability in IBM's Unix server space. With it, users would be able to slice and dice individual Power5 processors to create up to 10 partitions.
At the highest end, users would be able to create up to 512 partitions on a 64-processor system, Freund said.
The 0.13-micron Power5 chips also feature an acceleration technology that optimised performance in some applications. Freund said. The technology would allow certain commonly used code executed by software in many popular applications to be executed much faster by the processor hardware. Enabling the processor to take over tasks currently done by software would deliver significant performance benefits.
The first systems based on the new chip would start shipping sometime in the second half of 2004, IBM said.