IBM triples transistor performance with germanium

IBM triples transistor performance with germanium

IBM has successfully demonstrated a new technique for improving transistor performance that will help the company build smaller, more powerful chips in the next decade, company researchers said Monday.

The company has discovered a way to use germanium to improve the flow of electrons through its transistors, said Huiling Shang, a research staff member at IBM. A layer of strained germanium was applied directly to the channel of the transistor, or the area through which electrical current passes, in order to open up additional space for electrons within the channel.

Transistors built with strained germanium should have three times the performance of conventional transistors, Shang said.

Germanium has been used in smaller doses by several companies, including IBM, in an existing manufacturing technique called strained silicon. In this technique, a mixture of germanium and silicon is placed next to a layer of pure silicon, which causes the silicon atoms to stretch in order to align themselves with the silicon germanium atoms. This opens a wider path that allows more electrons to flow through the circuit.

Researchers have long known that germanium is a better conductor of electricity than silicon, but they had not figured out how to build higher concentrations of germanium into chips using conventional techniques, Shang said. IBM has accomplished this, and has also figured out how to strain the germanium layer in order to further improve performance, she said.

Germanium, which is a by-product of zinc ore processing, is a hard element with the same crystal structure as a diamond. It is a semiconductor with electrical properties between those produced by a metal and an insulator. Its use as a transistor was key in the advancement of solid-state electronics.

IBM will present additional details about how it accomplished its feat with germanium at the 2004 International Electron Devices Meeting (IEDM) in San Francisco next week, Shang said.

The technique gives chipmakers another resource to improve performance as shrinking the transistor becomes more difficult, Shang said. The technique is still in the research stage, but IBM believes it could be used on the 32 nanometer process generation, currently scheduled for introduction around 2013.

Chip designers have improved performance for several years by making smaller and smaller transistors. Smaller transistors are generally faster, and more of them can fit on a chip. However, transistors have now become so small that electrical current can leak out of the transistors as heat, a problem that is quite evident at the current 90 nanometer process generation and is expected to get worse at the 65 nanometer process generation scheduled for introduction in 2005 and 2006. The number attached to the process generation refers to the width of the smallest circuit line within a chip.

Other chip-making techniques that go beyond simply shrinking the transistor are under investigation at companies such as IBM, Intel Corp., and others. For example, Intel plans to integrate tri-gate transistors by the end of the decade to help control current leakage.

Also on Monday, IBM claimed it had built and demonstrated the world's smallest stable SRAM (static RAM) cell. The company used advanced chip-making techniques to build the SRAM cells, which consist of six transistors. The cells are half the size of the smallest experimental cell built to date, and 10 times as small as SRAM cells available today, said Jack Hergenrother, a research staff member at IBM.

Chip companies generally build SRAM cells as test products for new manufacturing techniques or tools. SRAM is often used as cache memory, which improves the performance of a processor by storing frequently used data close to the processing unit.

The SRAM cells will also be presented next week at the IEDM meeting, Hergenrother said.

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