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AMD CTO: Port hardware, not software

AMD CTO: Port hardware, not software

After 30 years of asking software developers to port their applications to different hardware platforms, the industry should acknowledge that it is now easier to change hardware designs than software, said Advanced Micro Devices (AMD) Chief Technology Officer Fred Weber during a keynote at Microprocessor forum in San Jose, California.

Weber told attendees at the annual microchip conference that hardware engineers are today spending less and less effort on developing the machine language instruction sets of their microprocessors, and that they should instead focus on adapting chips so that they can run different types of software, which he referred to as the slow moving "glacier" of the IT industry.

"We think of software as easy to change," Weber said. "It's counter-intuitive to call software the glacier, but the reality of it is that it is."

Weber said that the x86 instruction set, used in chips by both AMD and Intel, was moving into a variety of new areas because hardware makers were finding ways to adapt AMD's processors to existing software. He cited the work being done by Tiquit to build a Windows-based personal digital assistant as an example of this kind of adaptation. X86 machines were now meeting with similar success in new areas like storage servers and networking devices, he added.

Sixty-four bit computing is also an area where AMD has ambitions, and it is one where the company hopes that its more pliant approach to software will give it an advantage. AMD's Opteron processors have been designed to perform optimally with the 32-bit x86 applications that dominate the desktop and low end of the server space. This is in contrast with AMD's rival, Intel, whose 64-bit Itanium processor is based on a new instruction set called EPIC (Explicitly Parallel Instruction Computing). Itanium processors can run x86 applications, but developers must recompile their x86 applications to take advantage of the EPIC instruction set.

According to Weber, between one per cent and five per cent of the transistors on a typical microprocessor are devoted to instruction set interpretation. The most challenging problems for chip engineers these days are in new areas like memory access, power management and security, he said.

"We've got an incredible amount of work to do, but it ain't in the instruction set," he said.

Though multi-core processors like Sun Microsystem' UltraSPARC V and IBM's Power5 have taken centre stage at this week's conference, Weber, whose company has yet to announce plans to produce a dual-core design, was cool on the idea.

"There's a huge amount of talk about threading and how wonderful threading is going to be," he said in an interview after his keynote. "Yes there's a lot of parallel stuff out there, but it only goes so far."

While multi-core chip designers may hope to take advantage of Moore's law, which states that the number of processors on a chip will double about every 18 months, engineers should also be mindful of another dictum, Amdahl's law, Weber said. Amdahl's law, which was coined by mainframe pioneer Gene Amdahl, describes the limit to the performance enhancements that parallel processing can provide.

Some of today's applications, like databases, may be able to take advantage of parallel processing, but there will always be legacy applications that cannot, and that means that the emerging multi-core chip architectures will not solve all problems, Weber said. "I think there is enough (legacy software) in every single enterprise that it really... limits you from moving forward to new architectural ideas," he said.

Weber declined to comment on AMD's dual-core plans, except to point out that AMD's Opteron processor has been designed to accommodate a dual-core architecture.

"We think multithreading will happen over time, it's of some value, but it's limited," he said.


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