Transmeta hopes to give Intel’s Pentium M processor a formidable competitor with the TM8000 Efficeon processor, unveiled last week at the Microprocessor Forum (MPF) in California.
Efficeon is the next generation of Transmeta’s TM5800 Crusoe processor, which received much critical praise when it was introduced in 2000, but not many notebook designers selected the chip outside of the Japanese market.
“Crusoe was not as responsive as customers would have liked,” said John Heinlein, director of systems marketing for Transmeta. Efficeon adds the performance those customers were looking for, and delivers a better balance of performance and power consumption than Crusoe, he said.
“They’ve incorporated a number of significant improvements (into Efficeon). They looked at the original design, and addressed a number of deficiencies,” said Kevin Krewell, senior editor of the Microprocessor Report, which sponsors the MPF.
Transmeta has already released a number of details about Efficeon’s specifications, but additional details were disclosed during co-founder and chief technology officer David Ditzel’s keynote address to MPF attendees.
Efficeon will be released at clock speeds ranging from 1GHz to 1.2GHz with 1MB of Level 2 cache, said Art Swift, director of marketing for Transmeta, in a briefing prior to Ditzel’s speech. The company is shipping samples to its customers right now, and expects to ship the processor in volume later this year, he said.
Pricing information has not been finalised, but the chip is expected to cost a little more than $US100 in quantities of 1000 units, Swift said.
Transmeta will offer versions of the chip with different clock speeds, cache sizes and packaging sizes, he said.
At 1.1GHz, Efficeon will dissipate seven watts of power, which means it can be used in system designs without a cooling fan, Heinlein said.
Low power consumption has always been Transmeta’s trademark. Its processors use code-morphing software to interpret x86 instructions and translate frequently used x86 instructions into the VLIW (very long instruction word) machine language used by the processor to execute those instructions. The x86 instruction set is the engine for Intel and AMD’s desktop and notebook processors, and is used by just about every PC outside of Apple’s designs.
On other chips, this translation process is completed by transistors on the chip, but by using software to translate and cache those instructions, the most complex tasks required of the processor are handled by software. This enables Transmeta to use fewer transistors on the processor, saving more power compared to other designs, Heinlein said.
However, Crusoe underperformed the competition, and while Transmeta’s customers appreciated the power savings, they wanted a more powerful processor, Heinlein said.
With Efficeon, Transmeta doubled the number of instructions the processor can translate in one clock cycle from four to eight. The company raised the maximum clock speed of the chip from 1GHz to 1.2GHz, and doubled the Level 2 cache.
Efficeon also includes a group of multimedia instructions that have shipped with Intel and AMD’s processors for years. The Streaming SIMD Extensions (SSE) and SSE2 instructions help boost the performance of multimedia applications optimised for those instructions, Heinlein said. With the improvements, Efficeon delivers about 50 per cent more performance than Crusoe at the same clock speed, Heinlein said.
Like Crusoe, Efficeon will be targeted at ultra-portable notebooks and Tablet PCs, Swift said. The performance gains will allow the chip to compete with Intel for more designs in the thin-and-light category, or notebooks with 12-inch and 14-inch displays, he said.
In the future, Transmeta expects that its transition to 90-nanometer technology using Fujitsu’s process technology will generate a 50 per cent boost in clock speed, Heinlein said. This will bring Efficeon to around 2GHz, in line with the current clock speeds of the Pentium M, he said.
The company is also working on a new version of its LongRun power management technology that will appear in future processors. Ditzel demonstrated LongRun2, a technique that varies the processor’s voltage and frequency during both active and standby modes, during his address to MPF attendees.