Cisco pushes 'network memory' to alleviate bottlenecks

Cisco pushes 'network memory' to alleviate bottlenecks

Engineer cited for work on combining load balancing, caching algorithms

A Cisco engineer has been recognized for his work on scaling router and switch performance with algorithms he developed at a start-up Cisco acquired three years ago.

Sundar Iyer was recently cited in Technology Review Magazine as an innovator, under the age of 35, in the area of scaling router performance. Iyer began exploring the topic during his doctoral work at Stanford University on "network memory" -- alleviating performance problems caused by router memory access and storage bottlenecks in 10/40/100Gbps networks.

Iyer then co-founded Nemo Systems in 2004, where he was CTO and principal architect. Cisco acquired Nemoin October 2005. Nemo's network memory algorithms will be implemented in 27 Cisco product instances slated for commercial availability in 2009 or early 2010, Iyer says.

The problem occurs in high-speed networks, including the Internet backbone. Packets arrive on routers much faster than commodity memory can support.

"Systems have to handle hundreds of thousands of tiny packets stored and accessed from memory at very high speeds," Iyer says.

On a 10Gbps link, for example, packets can arrive approximately every 50ns, while commodity memory -- for example, DRAM memory -- can only be accessed once every 50ns. Packets can also arrive in any order and require unpredictable, or random access to memory.

Yet it takes two memory operations per packet every 50ns on a 10Gbps link: one to write the packet, another to read. If the memory can only do one operation every 50ns, it can't keep up; and as link rates increase, the router vs. memory performance gap widens and the problem only becomes worse.

Then end result is that routers cannot support the needs of real-time applications such as voice, video conferencing, multimedia and gaming that require guaranteed performance because it cannot ensure that packets can be written to or read from memory on time, at high line rates.

But adding memory capacity in the form of specialized 10Gbps SRAMs or reduced latency DRAMs are "extremely high in cost and unwieldy" in the number of components and power required per system, Iyer says. They also are unable to keep up with 40Gbps rates, he says.

Moreover, they may not alleviate virus attacks that can infiltrate a system based on the packet memory management pattern. If the attacker figures out this pattern, they can repeat it over and over, causing router or switch memory to be overwhelmed.

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