Hitachi says it has developed the world's smallest and thinnest chip, just a fraction of the thickness of paper. The chip, which exists in working prototype form, is aimed at wireless ID applications.
The company presented details of the 0.15-millimeter square, 7.5 micron thick chip on Sunday at the IEEE International Solid-State Circuits Conference (ISSCC) in San Francisco.
Hitachi first introduced the line of tiny chips, which it calls the "Mu chip", several years ago. The version announced in 2001 and currently in production is 0.4mm square, and was used to provide intelligent watermarking for more than 22 million admission tickets to last year's World Exposition in Aichi, Japan.
The newly announced prototype has a quarter of the surface area and an eighth of the thickness of a chip announced in 2003, which is 0.3mm square and 60 microns thick. The size reduction makes it easier for the chips to be embedded in paper, while increasing productivity fourfold, Hitachi said. The new chip can be produced 10 times more efficiently than the version of the Mu chip currently in production.
Hitachi is chiefly targeting RFID applications for the chip, which uses an external antenna to receive 2.45GHz microwaves and transmits back a 128-bit unique ID number. The number is written into ROM during the fabrication process and can't be rewritten, according to the company.
In the World Expo trial, the admission ticket system had a 0.001 percent incidence of ticket recognition error, the company said. Other potential applications include security, logistics, transportation and traceability, as well as "amusement", Hitachi said.
The company achieved the size reduction over the 0.3mm chip by using a silicon-on-insulator (SOI) process, which consists of a silicon layer and an insulation layer. In previous chips each high-frequency element needed to be isolated to prevent interference, but the SOI process allows each element to be surrounded by insulator, so that the elements can be in close proximity.
The process also allowed the complete removal of the silicon layer on the reverse side of the SOI substrate, allowing for a thinner chip.