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TSMC says new chip making technique close to perfect

TSMC says new chip making technique close to perfect

TSMC has nearly perfected a new chip making technique designed to extend the life of current factory equipment and build ever more intricate semiconductors.

Taiwan Semiconductor Manufacturing (TSMC) has nearly finished perfecting a new chip making technique designed to extend the life of current factory equipment even as it builds ever more intricate semiconductors.

The company has revealed its work with immersion lithography, which uses water or another clear liquid to sharpen the image of a chip's blueprint, which is imprinted onto a silicon wafer, the round, flat discs from which chips are made. By fine tuning the process, far more powerful chips can be created.

Semiconductors designs are created much like the blueprint for a building, with transistors, gates and other parts placed in a precise order to enable the chip to execute a function, such as store data or process information. In general, the more densely these transistors and other parts can be made on a chip, the more powerful it is or the more functions can be added, such as a mobile phone chip that receives a signal as well as allowing the phone to take pictures.

Many chips can be made on one silicon wafer. For example, thousands of the latest DRAM chips can be made on a single 12-inch (300mm) wafer.

Using liquid as a medium in lithography created a number of challenges for chip manufacturers, including defects such as bubbles, watermarks, particles, particle-induced printing defects and resist residue, TSMC said. The company developed its own proprietary technique to reduce defects to within acceptable standards for mass chip production.

The company's test wafers had come out with as few as three defects per wafer, enabling it to understand the underlying causes of defects, TSMC said. Now that the company understood what causes defects, it could work to improve its production speed and gradually build up to volume manufacturing.

Immersion has another bonus for chipmakers, since it also extends the life of current-generation lithography machines, large, multi-million dollar camera-like devices used to imprint the blueprint of a chip onto the silicon wafer. The next generation of such machines is far from being ready for use in chip factories, so it's critical to the chip industry to extend the life of the current generation of lithography systems.

"Immersion is just one of the [chip production] techniques people will consider," a spokesperson for TSMC, J.H. Tzeng, said. TSMC would begin manufacturing chips with feature sizes as tiny as 45-nanometers using immersion lithography, most likely in a few years, he said.

The nanometer measurements are an indication of the size of transistors and other parts that are etched onto chips. The more transistors on a chip, and the closer they are together, the faster the chip can perform tasks.

The smallest feature size on chips being built today are 65-nanometer.

TSMC has already delivered chips made using 65-nanometer technology to customers for qualification, and recently listed five customers for 65-nanometer technology on a recent news release, including Broadcom, Freescale Semiconductor and Altera, which are all based in the US.


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