SAN FRANCISCO: Intel has announced several changes to its roadmap for server processors, delaying its first dual-core Itanium 2 processor and replacing a future multicore Xeon processor with a new design that eliminates the performance penalty of shared connections to a chipset.
Montecito, the dual-core version of the Itanium 2 processor, would not be available in large volumes until the middle of next year, instead of the early part of next year as originally planned, an Intel spokesperson, Scott McLaughlin, said.
While preliminary shipments of the processor were already under way, Intel decided to make a few changes to the chip in order to reach the company's standard for production level quality, McLaughlin said, declining to specify the nature of the changes.
But Montecito would no longer ship with Foxton, a sophisticated power-management technology, and the speed of its front-side bus connection to memory would run at 533MHz instead of the 667MHz speed originally scheduled for the design, he said.
Intel also had killed Whitefield, a multicore Xeon processor for servers with four or more processors, McLaughlin said.
It was being replaced by a new processor called Tigerton that would appear in 2007, the same timeframe in which Whitefield was expected to arrive.
Tigerton processors would use a high-speed interconnect technology that would allow each processor to connect directly to the server's chipset, McLaughlin said. Current Xeon processors in multiprocessor servers must share a front-side bus connection to the chipset in order to access data from system memory or I/O, a bottleneck that industry analysts have blamed for the current performance gap between Intel's server chips and AMD's Opteron processors.
Intel's next-generation architecture, announced by president and CEO, Paul Otellini, in August, will be used as the blueprint for Tigerton. This architecture is based on low-power design principles used to build Intel's Pentium M processor for notebooks.
Whitefield had been expected to help tip the performance battle back toward Intel in 2007, but Tigerton should be even more powerful, McLaughlin said.
AMD has enjoyed favourable reviews from industry analysts, and even companies such as HP, for the performance of its Opteron server processors as compared to Intel's Xeon chips.
Intel is not specifying exactly how the Tigerton processors will connect to the server's chipset, such as whether they will use integrated memory or I/O controllers or a next-generation interconnect technology that Intel has vaguely discussed at previous Intel Developer Forums.
The Caneland platform, or the combination of Tigerton and its related chipset, was not the design that would bring socket compatibility to Intel's Xeon and Itanium processors, McLaughlin said. Intel wanted to make a chipset that could accommodate either a Xeon processor or an Itanium processor, which will help reduce product development costs for both Intel and its partners.
That compatibility was slated to arrive along with Tukwila, a multicore Itanium 2 processor now scheduled to arrive in 2008 as a result of the Montecito delay, he said.