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Fujitsu has four-core Sparc processor on tap

Fujitsu has four-core Sparc processor on tap

Fujitsu is planning a quad-core processor for 2008 that builds on its forthcoming dual-core Sparc64 VI processor.

Fujitsu has unveiled plans for a quad-core processor based on the Sparc instruction set that is scheduled to appear in high-end Unix servers around 2008.

The Sparc64 VI+, code-named Jupiter, would incorporate four separate processing cores on a single chip, manager of enterprise server development at Fujitsu, Takumi Maruyama, said at the Fall Processor Forum sponsored by In-Stat/MDR. It would run at clock speeds of up to 2.7GHz and consume somewhere in the neighborhood of 120 watts of power at maximum effort, he said.

Fujitsu still has yet to ship the Sparc64 VI+ processor's predecessor, code-named Olympus or the Sparc64 VI, but has reached a crucial milestone in that chip's development. It has finalised the design of the Sparc64 VI processor, or "taped out" the processor in chip lingo, which means the manufacturing process can begin.

The dual-core Sparc64 VI processor lays the groundwork for the quad-core Sparc64 VI+ chip. Each core on the processors can handle two software threads at the same time, allowing the Sparc64 VI to handle four independent threads and the Sparc64 VI+ to handle eight threads.

Both processors would use the same bus technology for connecting the processor to memory, Maruyama said. In the multicore processor era, keeping the processors fed with data funnelled through a high-speed connection to memory wa essential to realising the potential of multiple processor cores.

Multiple cores are needed at this stage in processor development because transistors have finally gotten small enough to present a serious problem: current leakage. Transistors are now so small that electrical current can leak out of critical junctions as heat, a problem that became more and more apparent as chip makers tried to improve performance the old-fashioned way by increasing the clock speed of the chip.

Even though the four cores on the Sparc64 VI+ would share a single connection to memory, the bandwidth of that bus was sufficient to keep the cores running at maximum capacity, Maruyama said.

Multiple core chips are ideal for multithreaded software applications, which are becoming more and more prevalent. But Fujitsu's chip designers were still concerned with ensuring that single-threaded applications continued to benefit from new technology, Maruyama said.

The company is using a technique called VMT, or virtual multithreading, to maximize the performance of software threads moving through the chip.

If one thread needed information that it couldn't find in the on-chip cache memory, and therefore neededto request that data from the main memory, the Sparc64 VI processor could quickly switch to another thread that had all the data it needed, Maruyama said.

This prevented the processor from idling while waiting for the data from main memory, and should deliver a 20 per cent improvement in performance over older Sparc64 chips without this technology, he said.


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