The new architecture that will grace Intel's processors next year borrows many of the design philosophies that made its Pentium M processors a success, according to company executives.
In a rare show of restraint, Intel is not labelling its new architecture with a carefully selected code name.
The company wants users to focus on the processors and systems they power, not the brains behind the product, president and CEO, Paul Otellini, said at the Intel Developer Forum.
He confirmed plans to release new dual-core chips for desktops, notebooks and servers based on a common power-saving architecture.
The new architecture carries forward some of the technologies found within the Pentium 4's Netburst architecture, such as 64-bit technology and virtualisation features, vice-president in Intel's Digital Enterprise Group and general manager of desktop platforms, Stephen Smith, said.
However, the design laid out by Intel has much more in common with the company's Pentium M processor and its focus on saving power, analysts said. It will appear along with the introduction of the Merom processor for notebooks, the Conroe processor for desktops and the Woodcrest processor for servers in the second half of 2006. The Pentium 4 Netburst products were designed to reach ever faster clock speeds. In order to achieve these speeds, Intel lengthened the pipeline of the processor to 31 stages, almost three times the length of the pipeline in its Pentium III.
Processors with short pipelines do more work in each individual stage in order to produce the end result. This means that they run slower than processors with longer pipelines that only work on a small piece of data in each stage. Those chips, like the P4, must run very fast in order to get the same amount of work done as a chip with a shorter pipeline.
Hitting those speeds wasn't a problem for Intel until about 2003. The smaller transistors that accompanied the introduction of the 90-nanometre processing technology caused a serious power leakage problem, which was exacerbated by the fact that high-frequency processors use a great deal of power.
Intel's new architecture dials down the power and the clock speed by using only 14 stages to process data, Smith said. This means that the new chips will do more work per stage and can therefore run at slower clock speeds, he said.
Merom and the other new chips can also issue, or start processing, four instructions per clock cycle, Smith said. This is a significant improvement that allows the chip to do even more work per cycle than the Pentium M predecessor, principal analyst with Insight 64, Nathan Brookwood, said.
Another notable improvement in its new design is the ability of memory caches to share data. This was first designed into the Yonah dual-core mobile processor that is scheduled to be released in the first quarter of next year, but will be extended to all chips in 2006.
One glaring issue with Intel's processor designs left unaddressed is the company's bus technology used to connect the processor to memory. This vital link is seen by many analysts as overwhelmed by the processing requirements of dual-core processors.
Intel views the bus design of its chips as a separate issue from the architecture used to build them, vice-president and general manager of Intel's Mobility Group, Dadi Perlmutter, said.