AHEAD OF THE CURVE: The great PC rip and replace

AHEAD OF THE CURVE: The great PC rip and replace

Were it not for AMD's reinvention of the x86 system, I wouldn't be surprised to find that most IT buyers have the location of Dell's "go to checkout" button programmed into their fingers. The lack of a need to do a gear-grinding platform shift, much less a retroactive rip and replace, is the core attraction of x86 systems. At its heart, a 32-bit Xeon is surprisingly comparable to a one-chip Pentium Pro.

That's coming to an end. You may wave off my warning that Opteron would relegate other x86 systems to the recycle bin. But you will thank me later if you heed this advice: Make room for Vanderpool and Pacifica. These on-chip virtualisation technologies from Intel and AMD, respectively, mark the second of what will be several forks in the road that render your existing PCs incapable of delivering a crucial set of capabilities. The first fork was 64-bit: You cannot make a Pentium Pro run 64-bit code. In 2006 you'll be buying PCs that do what even today's 64-bit x86 processors can't do: hardware-assisted virtualisation.

Vanderpool will add the guts needed to support a true hypervisor on 64-bit Pentium desktop and Xeon server CPUs. Pacifica will do the same for AMD's Athlon 64 and Opteron lines. You'll be able to split one machine into two or five or 10 virtual machines with performance that will drop your jaw.

Why all the fuss? I talked with one of AMD's Pacifica engineers and was amazed by the elegant simplicity of its hardware-assisted virtualisation. A context switch occurs whenever the x86 CPU, at the OS's request, suspends one running process and activates another. This needs to occur so rapidly that the x86 is specially designed to accommodate it. A context is its view of its executing state as defined by processor registers and flags. Registers and flags tell a process what to execute next, what the outcome of its previously executed instruction was, and where it fits in the stack (a small block of memory for temporary storage), among a few other things. The x86 makes it easy to stash and retrieve its execution state, and that's how Windows and other OSes can manage thousands of context switches per second.

The hurdle that software virtualisation has to leap is the x86 processor's inadequate concept of context. A virtual machine's concept of context extends well beyond CPU registers and flags.

Pacifica and Vanderpool expand the CPU's notion of context to bring it much closer to the CPU state switch that virtualisation requires. The x86 CPU will, under OS or virtualisation engine control, handle wholesale CPU state switches almost as easily as the x86 handles context switches today. And by extending the concept of the trap - a "when a process tries to do this, jump to this code" that's mostly used for security - Pacifica (and likely Vanderpool, although I'm not up to speed on that yet) will allow a virtual machine to do something incredible: replace selected x86 instructions with vendor-written code. It will be possible, under these new architectures, to take multiple approaches to virtualisation that enlists the CPU's aid to degrees.

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