I’m well known for taking up fringe causes. I always believe the subjects that seem crazy even to me will end up being important. I just consider that part of my job is being — combination of seer and loon — a combination that qualifies me to occupy ARN’s opinion page.
Ordinarily, my attendance at the chip heads’ convention called Microprocessor Forum (MPF) would net about as much value for readers as a trip to Disneyland. I had a hunch about this conference, and following that hunch gave me a new seer badge to pin on my vest.
Outside chiphead circles, Transmeta is most recognised for its former celebrity employee, Linus Torvalds. Transmeta is no more of an IT headline hound than Dallas Semiconductor or Texas Instruments. Most chipmakers have little or no public presence. They are content to do their thing quietly and let their OEMs take all the glory.
That approach works well until one of two things happens: a new chip outshines everything the chipmaker’s OEMs have accomplished to date, or a little chipmaker somehow annoys (intentionally or otherwise) a much larger rival. Transmeta has done both with its new Efficeon processor. The Efficeon model that Transmeta co-founder, David Ditzel, introduced at MPF is called the TM8000, but let’s stick with the more evocative name. This x86-compatible CPU might escape notice as another entry in the “just as good as Intel, only cheaper” race. It isn’t price that sets Efficeon apart; Transmeta still has its initial processor, Crusoe, to hit that target. Instead, Efficeon aims at the elusive combination of low power, high throughput, and solid computing performance.
On the power tip, this chip consumes 7 watts running full tilt and mere milliwatts during idle cycles — for example, the delay between keystrokes — according to Transmeta. CPUs that are better able to sense when those idle periods occur, and to control which parts of the system can be ramped down while others remain at full power, will take us from three- and four-hour notebook batteries to batteries that last all day. Of greater interest to me are the power-efficient desktop, blade, and high-density servers that Efficeon makes possible.
It isn’t easy to get peripheral chips to co-operate in a CPU’s power reduction strategy. Efficeon’s system-in-a-chip design, common in embedded systems, plants the 400MHz double data rate memory, 4X AGP graphics and HyperTransport bus interfaces right on the CPU’s die.
Electrons don’t have far to drive to get to memory or to the display. What’s more, there aren’t any debates among elements of the chip set about how to reduce power because with Efficeon, the CPU chip is most of the chip set. Only distant peripherals such as PCI slots and USB ports are handled outside the Efficeon by a south bridge chip. And as a CPU alone, Efficeon meets modern requirements.
It has 1MB of level 2 cache, full compatibility with Intel’s SIMD (single instruction multiple data) vector math acceleration, and according to Transmeta, the ability to outperform Centrino at the same clock speed.
As always, the vendor claims it nailed all of its targets and it’s my job is to say “prove it”. Looking at Efficeon’s design, half the job of winning me over will be just showing me a working processor. I have only scratched the surface of Efficeon’s capabilities, and what little I’ve discussed here would still be an incredible stack of features to stuff into one dime-sized die. I will challenge Transmeta to prove its claims regarding Efficeon.
Meanwhile, I’ll polish my merit badge and be proud, in my humble way, that the world is coming around to my point of view.