Intel has demonstrated working static RAM (SRAM) chips with transistors built using the company's 65 nanometre process technology. Microprocessors built using the technology would be ready in 2005, the company said.
Intel use SRAM chips to test out its process technology because the chips were easy to design and troubleshoot, but the transistors would be used on new versions of products such as the Pentium 4 or Xeon, an Intel senior fellow and director of the company's process architecture and integration, Mark Bohr, said.
Products built on Intel's 90 nanometre process technology are expected to make their debut in the coming weeks. For the next generation of chips built at 65 nanometres, Intel would keep the strained silicon and copper interconnects used in 90 nanometre chips, Bohr said.
Strained silicon is a manufacturing technique in which a layer of silicon germanium is deposited on top of a silicon wafer. The atoms in each substance naturally seek to align themselves, which stretches the silicon, allowing more electrons to flow than was possible with just silicon.
Intel would also use eight layers of copper interconnects and a new low-k dielectric material on the 65 nanometre chips that reduced power consumption, Bohr said.
A material's "k" value refers to its ability to compress electrical fields, and a dielectric with a lower k value increases the speed at which electrons flow through a transistor.
The costs of moving to the 65 nanometre technology would be reduced by the ability to use much of the same lithography tools used to make the 90 nanometre chips, Bohr said.
Intel would purchase some upgraded tools to help build some of the new structures, but most of the tools would remain the same, he said.
The 65 nanometre chips would be produced at Intel's facility in Hillsboro, Oregon, and rolled out to the company's other manufacturing plants over time, Bohr said.
Intel recently announced it was moving to a new high-k dielectric material as well as metal gates on its 45 nanometre process technology.
The discovery of that material came too late to include in this process technology, Bohr said.
The high-k material is necessary at the 45 nanometre level to prevent current leakage caused by the extreme thinness of the chip's structures at 45 nanometres, Intel said last month.